# Output products list for <mig_39>
_xmsgs\pn_parser.xmsgs
mig_39.gise
mig_39.vho
mig_39.xco
mig_39.xise
mig_39\docs\ug388.pdf
mig_39\docs\ug416.pdf
mig_39\example_design\datasheet.txt
mig_39\example_design\log.txt
mig_39\example_design\mig.prj
mig_39\example_design\par\create_ise.bat
mig_39\example_design\par\example_top.ucf
mig_39\example_design\par\icon_coregen.xco
mig_39\example_design\par\ila_coregen.xco
mig_39\example_design\par\ise_flow.bat
mig_39\example_design\par\ise_run.txt
mig_39\example_design\par\makeproj.bat
mig_39\example_design\par\mem_interface_top.ut
mig_39\example_design\par\readme.txt
mig_39\example_design\par\rem_files.bat
mig_39\example_design\par\set_ise_prop.tcl
mig_39\example_design\par\vio_coregen.xco
mig_39\example_design\rtl\example_top.vhd
mig_39\example_design\rtl\iodrp_controller.vhd
mig_39\example_design\rtl\iodrp_mcb_controller.vhd
mig_39\example_design\rtl\mcb_raw_wrapper.vhd
mig_39\example_design\rtl\mcb_soft_calibration.vhd
mig_39\example_design\rtl\mcb_soft_calibration_top.vhd
mig_39\example_design\rtl\memc3_infrastructure.vhd
mig_39\example_design\rtl\memc3_tb_top.vhd
mig_39\example_design\rtl\memc3_wrapper.vhd
mig_39\example_design\rtl\traffic_gen\afifo.vhd
mig_39\example_design\rtl\traffic_gen\cmd_gen.vhd
mig_39\example_design\rtl\traffic_gen\cmd_prbs_gen.vhd
mig_39\example_design\rtl\traffic_gen\data_prbs_gen.vhd
mig_39\example_design\rtl\traffic_gen\init_mem_pattern_ctr.vhd
mig_39\example_design\rtl\traffic_gen\mcb_flow_control.vhd
mig_39\example_design\rtl\traffic_gen\mcb_traffic_gen.vhd
mig_39\example_design\rtl\traffic_gen\rd_data_gen.vhd
mig_39\example_design\rtl\traffic_gen\read_data_path.vhd
mig_39\example_design\rtl\traffic_gen\read_posted_fifo.vhd
mig_39\example_design\rtl\traffic_gen\sp6_data_gen.vhd
mig_39\example_design\rtl\traffic_gen\tg_status.vhd
mig_39\example_design\rtl\traffic_gen\v6_data_gen.vhd
mig_39\example_design\rtl\traffic_gen\wr_data_gen.vhd
mig_39\example_design\rtl\traffic_gen\write_data_path.vhd
mig_39\example_design\sim\functional\ddr2_model_c3.v
mig_39\example_design\sim\functional\ddr2_model_parameters_c3.vh
mig_39\example_design\sim\functional\isim.bat
mig_39\example_design\sim\functional\isim.tcl
mig_39\example_design\sim\functional\mig_39.prj
mig_39\example_design\sim\functional\readme.txt
mig_39\example_design\sim\functional\sim.do
mig_39\example_design\sim\functional\sim_tb_top.vhd
mig_39\example_design\synth\example_top.lso
mig_39\example_design\synth\example_top.prj
mig_39\example_design\synth\mem_interface_top_synp.sdc
mig_39\example_design\synth\script_synp.tcl
mig_39\user_design\datasheet.txt
mig_39\user_design\log.txt
mig_39\user_design\mig.prj
mig_39\user_design\par\create_ise.bat
mig_39\user_design\par\icon_coregen.xco
mig_39\user_design\par\ila_coregen.xco
mig_39\user_design\par\ise_flow.bat
mig_39\user_design\par\ise_run.txt
mig_39\user_design\par\makeproj.bat
mig_39\user_design\par\mem_interface_top.ut
mig_39\user_design\par\mig_39.ucf
mig_39\user_design\par\readme.txt
mig_39\user_design\par\rem_files.bat
mig_39\user_design\par\set_ise_prop.tcl
mig_39\user_design\par\vio_coregen.xco
mig_39\user_design\rtl\iodrp_controller.vhd
mig_39\user_design\rtl\iodrp_mcb_controller.vhd
mig_39\user_design\rtl\mcb_raw_wrapper.vhd
mig_39\user_design\rtl\mcb_soft_calibration.vhd
mig_39\user_design\rtl\mcb_soft_calibration_top.vhd
mig_39\user_design\rtl\memc3_infrastructure.vhd
mig_39\user_design\rtl\memc3_wrapper.vhd
mig_39\user_design\rtl\mig_39.vhd
mig_39\user_design\sim\afifo.vhd
mig_39\user_design\sim\cmd_gen.vhd
mig_39\user_design\sim\cmd_prbs_gen.vhd
mig_39\user_design\sim\data_prbs_gen.vhd
mig_39\user_design\sim\ddr2_model_c3.v
mig_39\user_design\sim\ddr2_model_parameters_c3.vh
mig_39\user_design\sim\init_mem_pattern_ctr.vhd
mig_39\user_design\sim\isim.bat
mig_39\user_design\sim\isim.tcl
mig_39\user_design\sim\mcb_flow_control.vhd
mig_39\user_design\sim\mcb_traffic_gen.vhd
mig_39\user_design\sim\memc3_tb_top.vhd
mig_39\user_design\sim\mig_39.prj
mig_39\user_design\sim\rd_data_gen.vhd
mig_39\user_design\sim\read_data_path.vhd
mig_39\user_design\sim\read_posted_fifo.vhd
mig_39\user_design\sim\readme.txt
mig_39\user_design\sim\sim.do
mig_39\user_design\sim\sim_tb_top.vhd
mig_39\user_design\sim\sp6_data_gen.vhd
mig_39\user_design\sim\tg_status.vhd
mig_39\user_design\sim\v6_data_gen.vhd
mig_39\user_design\sim\wr_data_gen.vhd
mig_39\user_design\sim\write_data_path.vhd
mig_39\user_design\synth\mem_interface_top_synp.sdc
mig_39\user_design\synth\mig_39.lso
mig_39\user_design\synth\mig_39.prj
mig_39\user_design\synth\script_synp.tcl
mig_39_flist.txt
mig_39_readme.txt
mig_39_xmdf.tcl
